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International Conference Papers

1

K.-J. Chen, W.-M. Chen, L.-Y. Tang, Y.-T. Cheng, Ming-Dou Ker, and C.-Y. Wu

A 13.56 MHz metamaterial for the wireless power transmission enhancement in implantable biomedical devices,”

Proc. of 2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems & Eurosensors XXXIII, Berlin, Germany, Jun 23-27. 2019.

2

T.-Y. Hung and Ming-Dou Ker

ESD protection design of high-linearity SPDT CMOS T/R switch for cellular applications,”

Proc. of 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 26-29. 2019.

3

C.-C. Chen and Ming-Dou Ker

Investigation on latch-up path between I/O PMOS and core PMOS in a 0.18-µm CMOS process,”

Proc. of 2019 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, Mar. 31 - Apr. 4, 2019.

4

S.-P. Lin and Ming-Dou Ker

Design of multiple-charge-pump system for implantable biomedical applications,”

Proc. of the IEEE Biomedical Circuits and System Conference (BioCAS), Cleveland, USA, Oct. 17-19, 2018.

5  

W.-C. Chen and Ming-Dou Ker

Surge protection design with surge-to-digital converter for microelectronic circuits and systems,”

Proc. of the 29th European Symposium on Reliability of Electron Device, Failure Physics and Analysis (ESREF), Aalborg, Denmark, Oct. 1-5, 2018.

6

C.-T. Dai, Ming-Dou Ker, Y.-N. Jou, S.-C. Huang, G.-L. Lin, and J.-H. Lee

Study on latchup path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD technology,”

Proc. of the 40th Annual Electrical Overstress/Electrostatic Discharge Symposium, Reno, NV, USA, Sep. 23-28, 2018.

7

J.-T. Chen and Ming-Dou Ker

Power-rail ESD clamp circuit with polysilicon diodes against false trigger during fast power-on events,”

Proc. of the 40th Annual Electrical Overstress/Electrostatic Discharge Symposium, Reno, NV, USA, Sep. 23-28, 2018.

8

C.-C. Hsieh and Ming-Dou Ker

Design of multi-channel monopolar biphasic stimulator for implantable biomedical applications,”

Proc. of the IEEE 61th International Midwest Symposium on Circuit and Systems, Windsor, Canada, Aug. 5-8, 2018.

9

W.-C. Chen and Ming-Dou Ker

On-chip transient detection circuit for microelectronic systems against electrical transient disturbances due to ESD events,”

Proc. of the IEEE Region 10 Symposium (TENSYMP), Sydney, Australia, Jul. 4-6, 2018.

10

X.-R. Kang and Ming-Dou Ker

New on-chip transient detection circuit to improve electromagnetic susceptibility of microelectronic systems,”

Proc. of the 13th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, Oct. 18-20, 2017. (DOI: 10.1109/EDSSC.2017.8126515)

11

Ming-Dou Ker, C.-Y. Lin, Y.-H. Wu, and W.-T. Wang

ESD protection design with low-leakage consideration for silicon chips of IoT applications,”

Proc. of the 7th Annual IEEE Int. Conf. on CYBER Technology in Automation, Control, and Intelligent Systems (IEEE-CYBER), Hawaii, USA, Jul. 31-Aug. 4, 2017. (DOI: 10.1109/CYBER.2017.8446566)

12  

C.-H. Cheng, Ming-Dou Ker, C.-Y. Lee, Y.-L. Hsin, S.-F. Liang, F.-Z. Shaw, and C.-Y. Wu

“The brain mapping system design with closed-loop stimulation capability for seizure onset region mapping and control for epileptic patients,”

Proc. of the 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC'17), Je-Ju Island, Korea, Jul. 11-15, 2017.

13

Ming-Dou Ker, P.-Y. Chiu, W.-T. Shieh, and C.-C. Wang

ESD-induced latchup-like failure in a touch panel control IC,”

Proc. of the 24th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Chengdu, China, Jul. 4-7, 2017. (DOI: 10.1109/IPFA.2017.8060061)

14

T.-Y. Hung and Ming-Dou Ker

ESD protection design on T/R switch with embedded SCR in CMOS process,”

Proc. of the 24th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Chengdu, China, Jul. 4-7, 2017. (DOI: 10.1109/IPFA.2017.8060079)

15

C. Chiang, P.-C. Chang, M.-L. Chao, T.-H. Tang, K.-C. Su, and Ming-Dou Ker

Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering,”

Proc. of the 24th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Chengdu, China, Jul. 4-7, 2017. (DOI: 10.1109/IPFA.2017.8060226)

16

C.-H. Cheng, P.-Y. Tsai, T.-Y. Yang, W.-H. Cheng, T.-Y. Yen, Z. Luo, X.-H. Qian, Z.-X. Chen, T.-H. Lin, W.-H. Chen, W.-M. Chen, S.-F. Liang, F.-Z. Shaw, C.-S. Chang, F.-Y. Shih, Y.-L. Hsin, C.-Y. Lee, Ming-Dou Ker, and C.-Y. Wu

“A fully integrated closed-loop neuromodulation SoC with wireless power and bi-directional data telemetry for real-time human epileptic seizure control,”

Digest of Technical Paper of 2017 IEEE Symposium on VLSI  Circuits, Kyoto, Japan, Jun. 5-8, 2017, pp. C44-C45. (DOI: 10.23919/VLSIC.2017.8008541)

17

X.-H. Qian, Y.-C. Wu, T.-Y. Yang, C.-H. Cheng, H.-C. Chu, W.-H. Cheng, T.-Y. Yen, T.-H. Lin, Y.-J. Lin, Y.-C. Lee, J.-H. Chang, S.-T. Lin, S.-H. Li, T.-C. Wu, C.-C. Huang, C.-F. Lee, C.-H. Yang, C.-C. Hung, T.-S. Chi, C.-H. Liu,

Ming-Dou Ker, and C.-Y. Wu

“A bone-guided cochlear implant CMOS microsystem preserving acoustic hearing,”

Digest of Technical Paper of 2017 IEEE Symposium on VLSI  Circuits, Kyoto, Japan, Jun. 5-8, 2017, pp. C46-C47. (DOI: 10.23919/VLSIC.2017.8008542)

18

C.-T. Dai, S.-H. Chen, D. Linten, M. Scholz, G. Hellings, R. Boschke, J. Karp, M. Hart, G. Groeseneken, Ming-Dou Ker, A. Mocuta, and N. horiguchi

Latchup in bulk FinFET technology,

Proc. of 2017 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, Apr. 2-6, 2017.

19

“Design considerations and clinical applications of closed-loop neural disorder control SoCs,”

C.-Y. Wu, C.-H. Cheng, Y.-H. Ou-Yang, C.-C. Chen, W.-M. Chen, Ming-Dou Ker, C.-Y. Lee, S.-F. Liang, and F.-Z. Shaw

Proc. of 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba/Tokyo, Japan, Jan. 16-19, 2017.

20

“ESD protection design for high-speed applications in CMOS technology,”

J.-T. Chen, C.-Y. Lin, R.-K. Chang, Ming-Dou Ker, T.-C. Tzeng, and T.-C. Lin

Proc. of 59th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, United Arab Emirates, Oct. 16-19, 2016.

21

“Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator,”

Z. Luo, and Ming-Dou Ker

Proc. of IEEE International NEWCAS conference, Vancouver, Canada, Jun. 26-29, 2016.

22

“A gigahertz low-noise amplifier with ESD protection in nanoscale CMOS technology,”

C.-Y. Lin, R.-K. Chang, and Ming-Dou Ker

Proc. of 7th IEEE Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), Shenzhen, China, May 18-21, 2016, pp. 60.

23

“On-chip ESD protection design for HV integrated circuits (invited talk),”

Ming-Dou Ker

Proc. of 2016 IEEE International Nanoelectronics conference (INEC), Chengdu, China, May 9-11, 2016

24

“A 70nW, 0.3V temperature compensation voltage reference consisting of subthreshold MOSFETs in 65nm CMOS technology,”

T.-C. Lu, Ming-Dou Ker, and H.-W. Zan

Proc. of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 25-27, 2016.

25

ESD self-protection design on 2.4-GHz T/R switch for RF application in CMOS process,”

C.-Y. Lin, R.-H. Liu, and Ming-Dou Ker

Proc. of 2016 IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, USA, Apr. 17-21, 2016.

26

ESD protection design with latchup-free immunity in 120V SOI process,”

Y.-J. Huang, Ming-Dou Ker, Y.-J. Huang, C.-C. Tsai, Y.-N. Jou, and G.-L. Lin

Proc. of  IEEE International SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S), Rohnert Park, California, USA, Oct. 5-8, 2015.

27

Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology,”

C.-Y. Lin, Ming-Dou Ker, P.-H. Chang, and W.-T. Wang

Proc. of 10th IEEE Nanotechnology Materials and Devices Conference (NMDC), Anchorage, Alaska, USA, Sep. 13-15, 2015, pp. 63-66.

28

ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC,”

C.-T. Dai and Ming-Dou Ker

Proc. of 28th IEEE International System-on-Chip Conference (SOCC), Beijing, China, Sep. 8-11, 2015, pp. 380-383.

29

Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection,”

S.-F. Liao, K.-N. Tang, Ming-Dou Ker, J.-R. Yeh, H.-C. Chiou, Y.-J. Huang, C.-C. Tsai, Y.-N. Jou, and G.-L. Lin

Proc. of 22nd IEEE European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, Aug. 24-26, 2015.

30

Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits,”

H.-W. Tsai and Ming-Dou Ker

Proc. of 22nd IEEE European Conference on Circuit Theory and Design (ECCTD), Trondheim, Norway, Aug. 24-26, 2015.

31

Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology,”

C.-Y. Lin, P.-H. Chang, R.-K. Chang, Ming-Dou Ker, and W.-T. Wang

Proc. of IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Hsinchu, Taiwan, Jun. 29-Jul. 2, 2015.

32

Improve latch-up immunity by circuit solution,”

H.-W. Tsai and Ming-Dou Ker

Proc. of IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Hsinchu, Taiwan, Jun. 29-Jul. 2, 2015.

33

“Active ESD protection for input transistors in a 40-nm CMOS process,”

F. A. Altolaguirre and Ming-Dou Ker

Proc. of IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 2015, pp. 162-165.

34

“Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process,”

F. A. Altolaguirre and Ming-Dou Ker

Proc. of 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), College Station, Texas, USA, Aug. 3-6, 2014, pp. 250-253.

35

“A closed-loop neural-prosthetic device for real-time epileptic seizure control,”

C.-Y. Wu, H. Chiueh, Ming-Dou Ker, Y.-L. Hsin, S.-F. Liang, F.-Z. Shaw, T.-J. Chen, C.-Y. Lin, Y.-L. Wang, W.-M. Chen, and W. Liu

Proc. of 41st Neural Interfaces Conference, Dallas, Texas, USA, Jun. 23-25, 2014.

36

“Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS,”

C.-Y. Lin, M.-L Fan, Ming-Dou Ker, L.-W Chu, J.-C Tseng, and M.-H. Song

Proc. of 2014 IEEE International Reliability Physics Symposium, Waikoloa, Hawaii, USA, Jun. 1-5, 2014.

37

“Study on ESD protection design with stacked low-voltage devices for high-voltage applications,”

C.-T. Dai and Ming-Dou Ker

Proc. of 2014 IEEE International Reliability Physics Symposium, Waikoloa, Hawaii, USA, Jun. 1-5, 2014.

38

“Improvement on CDM ESD robustness of high-voltage tolerant nLDMOS SCR devices by using differential doped gate,”

S.-H. Chen, D. Linten, M. Scholz, G. Hellings, R. Boschke, G. Groeseneken, Y.-C. Huang, and Ming-Dou Ker

Proc. of 2014 IEEE International Reliability Physics Symposium, Waikoloa, Hawaii, USA, Jun. 1-5, 2014.

39

A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant,”

K.-Y. Lin, Ming-Dou Ker, and C.-Y. Lin

Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, Jun. 1-5, 2014, pp. 237-240.

40

ESD protection design for wideband RF applications in 65-nm CMOS process,”

L.-W. Chu, C.-Y. Lin, Ming-Dou Ker, M.-H. Song, J.-C. Tseng, C.-P. Jou, and M.-H. Tsai

Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, Jun. 1-5, 2014, pp. 1480-1483.

41

“ESD-Transient detection circuit with equivalent Capacitance-Coupling detection mechanism and high efficiency of layout area in a 65nm CMOS technology,”

C.-T. Yeh and Ming-Dou Ker

Proc. of 2013 Electrical Overstress / Electrostatic Discharge (EOS/ESD) Symposium, Las Vegas, NV, USA, Sep. 8-13, 2013, pp. 71-77.

42

“Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology,”

P.-Y. Chiu and Ming-Dou Ker

Proc. of 26th IEEE International System-on-Chip Conference (SOCC), Erlangen, Germany, Sep. 4-6, 2013, pp. 33-36.

43

“ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology,”

C.-Y. Lin, L.-W. Chu, S.-Y. Tsai, Ming-Dou Ker, M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C. Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, Y.-L. Wei, and T.-H. Chang

Proc. of IEEE International Conference on Nanotechnology, Beijing, China, Aug. 5-8, 2013, pp. 241-244.

44

“On-chip ESD protection designs in RF integrated circuits for radio and wireless applications,”

Ming-Dou Ker and C.-Y. Lin

Proc. of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Jun. 3-5, 2013.

45

“SCR device for on-chip ESD protection in RF power amplifier,”

C.-Y. Lin and Ming-Dou Ker

Proc. of IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, China, Jun. 3-5, 2013.

46

“Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology,”

F. A. Altolaguirre and Ming-Dou Ker

Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, May 19-23, 2013, pp. 2638-2641.

47

“ESD and EOS impacts during module assembly processes for display panels,”

T.-Y. Chen and Ming-Dou Ker

Digest of Technical Paper, SID International Symposium, Seminar, and Exhibition, Vancouver, Canada, May 19-24, 2013, pp. 302-305.

48

“Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process,”

C.-T. Yeh and Ming-Dou Ker

Proc. of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 22-24, 2013, pp. 25-28.

49

“Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits,”

H.-W. Tsai, Ming-Dou Ker, Y.-S. Liu, and M.-N. Chuang

Proc. of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 22-24, 2013, pp. 33-36.

50

“Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology,”

F. A. Altolaguirre and Ming-Dou Ker

Proc. of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 22-24, 2013, pp. 270-273.

51

Resistor-less power-rail ESD clamp circuit with ultra-low leakage current in 65nm CMOS process,”

C.-T. Yeh and Ming-Dou Ker

Proc. of 2013 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, Apr. 14-18, 2013.

52

Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-well test structures,”

C.-T. Dai and Ming-Dou Ker

Proc. of IEEE International Conference on Microelectronics Test Structures (ICMTS), Osaka, Japan, Mar. 25-28, 2013, pp. 127-130.

53

“Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process,”

Y.-C. Huang, C.-T. Dai, and Ming-Dou Ker

Proc. of IEEE International Symposium on Next-Generation Electronics (ISNE), Kaohsiung, Taiwan, Feb. 25-26, 2013, pp. 116-119.

54

A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control,”

W.-M. Chen, H. Chiueh, T.-J. Chen, C.-L. Ho, C. Jeng, S.-T. Chang, Ming-Dou Ker, C.-Y. Lin, Y.-C. Huang, C.-W. Chou, T.-Y. Fan, M.-S. Cheng, S.-F. Liang, T.-C. Chien, S.-Y. Wu, Y.-L. Wang, F.-Z. Shaw, Y.-H. Huang, C.-H. Yang, J.-C. Chiou, C.-W. Chang, L.-C. Chou, C.-Y. Wu

Technical Digest of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 17- 21, 2013, pp. 286-287.

55

A 56-67 GHz low-noise amplifier with 5.1-dB NF and 2.5-kV HBM ESD protection in 65-nm CMOS,”

M.-H. Tsai, H.-H. Hsieh, C.-Y. Lin, L.-W. Chu, S.-H. Hsu, J.-D. Jin, T.-J. Yeh, C.-P. Jou, F.-L. Hsueh, and Ming-Dou Ker

Proc. of Asia-Pacific Microwave Conference (APMC), Kaohsiung, Taiwan, Dec. 4-7, 2012, pp. 747-749.

56

Design of ESD protection for RF CMOS power amplifier with inductor in matching network,”

S.-Y. Tsai, C.-Y. Lin, L.-W. Chu, and Ming-Dou Ker

Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Kaohsiung, Taiwan, Dec. 2-5, 2012, pp. 467-470.

57

Design of negative high voltage generator for biphasic stimulator with SoC integration consideration,”

Y.-C. Huang, Ming-Dou Ker, and C.-Y. Lin

Proc. of IEEE Biomedical Circuits and Systems (BioCAS) Conference, Hsinchu, Taiwan, Nov. 28-30, 2012, pp. 29-32.

58

Live Demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability,”

Ming-Dou Ker, W.-L. Chen, and C.-Y. Lin

Proc. of IEEE Biomedical Circuits and Systems (BioCAS) Conference, Hsinchu, Taiwan, Nov. 28-30, 2012, p. 78.

59

Design of AC-coupled circuit for high-speed interconnects,”

C.-W. Huang, K.-J. Liu, Y.-J. Huang, M.-K. Chen, Y.-L. Lin, and Ming-Dou Ker

Proc. of IEEE Global High Tech Congress on Electronics (GHTCE), Kaohsiung, Taiwan, Nov. 18-20, 2012, pp. 87-90.

60

Design of ESD protection cell for dual-band RF applications in a 65-nm CMOS process,”

L.-W. Chu, C.-Y. Lin, S.-Y. Tsai, Ming-Dou Ker, M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C. Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, T.-H. Chang, and Y.-L. Wei

Proc. of Electrical Overstress / Electrostatic Discharge (EOS/ESD) Symposium, Tucson, Arizona, USA, Sep. 9-14, 2012, pp. 331-335.

61

Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process,”

C.-T. Dai, P.-Y. Chiu, Ming-Dou Ker, F.-Y. Tsai, Y.-H. Pan, and C.-K. Tsai

Proc. of  International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 2-7, 2012.

62

A neural prosthetic device with closed-loop epileptic seizure detection and conditional therapeutic stimulation,”

C.-Y. Wu, Y.-L. Hsin, S.-F. Liang, F.-Z. Shaw, J.-C. Chiou, Ming-Dou Ker, and H. Chiueh

Proc. of Neural Interfaces Conference (NIC), Salt Lake City, Utah, USA, Jun. 18-20, 2012, p. 255.

63

Design of high-voltage-tolerant stimulus driver for epileptic seizure suppression in a 0.18-μm CMOS process,”

C.-Y. Lin, Y.-J. Li, Y.-C. Huang, and Ming-Dou Ker

Proc. of Neural Interfaces Conference (NIC), Salt Lake City, Utah, USA, Jun. 18-20, 2012, p. 154.

64

New design of transient-noise detection circuit with SCR device for system-level ESD protection,”

Ming-Dou Ker and W.-Y. Lin

Proc. of IEEE International NEWCAS Conference, Montreal, Canada, Jun. 17-20, 2012, pp. 81-84.

65

High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-μm CMOS process,”

C.-Y. Lin, Y.-J. Li, and Ming-Dou Ker

Proc. of 10th IEEE International NEWCAS Conference, Montreal, Canada, Jun. 17-20, 2012, pp. 125-128.

66

Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology,”

L.-W. Chu, C.-Y. Lin, S.-Y. Tsai, Ming-Dou Ker, M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C. Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, and T.-H. Chang

Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Seoul, Korea, May 20-23, 2012, pp. 2127-2130.

67

Study of voltage-step dependency on TLP-measured secondary breakdown current (It2) of ESD clamp circuit in a 16-V double-diffused drain MOS (DDDMOS) process,”

C.-T. Dai, P.-Y. Chiu, Ming-Dou Ker, F.-Y. Tsai, Y.-H. Pan, and C.-K. Tsai

Presentations of International Electrostatic Discharge Workshop (IEW), Priory Corsendonk, Oud-Turnhout, Belgium, May 14-17, 2012.

68

New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process,”

C.-T. Yeh and Ming-Dou Ker

Proc. of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 23-25, 2012.

69

ESD protection structure with inductor-triggered SCR for RF applications in 65-nm CMOS process,”

C.-Y. Lin, L.-W. Chu, Ming-Dou Ker, M.-H. Song, C.-P. Jou, T.-H. Lu, J.-C. Tseng, M.-H. Tsai, T.-L. Hsu, P.-F. Hung, and T.-H. Chang

Proc. of IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, USA, Apr. 15-19, 2012.

70

“ESD-aware circuit design in CMOS integrated circuits to meet system-level ESD specification in microelectronic systems,” (invited paper)

Ming-Dou Ker

Proc. of 2011 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Tianjin, China, Nov. 17-18, 2011.

71

“PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit,”

C.-T. Yeh, Y.-C. Liang, and Ming-Dou Ker

Proc. of 2011 Electrical Overstress / Electrostatic Discharge (EOS/ESD) Symposium, Anaheim, CA, USA, Sep. 11-16, 2011, pp. 1-6.

72

“Modified LC-tank ESD protection design for 60-GHz RF applications,”

C.-Y. Lin, L.-W. Chu, S.-Y. Tsai, Ming-Dou Ker, T.-H. Lu, T.-L. Hsu, P.-F. Hung, M.-H. Song, J.-C.Tseng, T.-H. Chang, and M.-H. Tsai

Proc. of 20th European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, Aug. 29-31, 2011, pp. 57-60.

73

“ESD protection consideration in nanoscale CMOS technology,”

Ming-Dou Ker and C.-Y. Lin

Proc. of 2011 IEEE International Conference on Nanotechnology (IEEE-NANO), Portland, Oregon, USA, Aug. 15-18, 2011, pp. 720-723.

74

“Overview on the design of low-leakage power-rail ESD clamp circuits in nanoscale CMOS processes,” (invited paper)

F. A. Altolaguirre and Ming-Dou Ker

Proc. of 2011 Argentine School of Micro-Nanoelectronics Technology and Applications (EAMTA), Buenos Aires, Argentina, Aug. 11-12, 2011.

75

“Design of digital time-modulation pixel memory circuit on glass substrate for low power application,”

S.-H. Chen, Ming-Dou Ker, and T.-M. Wang

Proc. of 2011 SID International Symposium, Seminar, and Exhibition, Los Angeles, USA, May 15-20, 2011, pp. 1281-1284.

76

“Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events,”

C.-T. Yeh, Y.-C. Liang, and Ming-Dou Ker

Proc. of 2011 IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011, pp. 1403-1406.

77

“Adaptable stimulus driver for epileptic seizure suppression,”

Ming-Dou Ker, W.-L. Chen, and C.-Y. Lin

Proc. of 2011 International Conference on Integrated Circuit Design & Technology (ICICDT), Kaohsiung, Taiwan, May 2-4, 2011.

78

“Design of low-leakage power-rail ESD clamp circuit with MOM capacitor in a 65-nm CMOS process,”

P.-Y. Chiu and Ming-Dou Ker

Proc. of 2011 International Conference on Integrated Circuit Design & Technology (ICICDT), Kaohsiung, Taiwan, May 2-4, 2011

79

“Transient-to-digital converter to detect electrical fast transient (EFT) disturbance for system protection design,”

C.-C. Yen, W.-Y. Lin, Ming-Dou Ker, C.-L. Tsai, S.-F. Chen, and T.-Y. Chen

Proc. of 2011 International Conference on Integrated Circuit Design & Technology (ICICDT), Kaohsiung, Taiwan, May 2-4, 2011

80

“Layout styles to improve CDM ESD robustness of integrated circuits in 65-nm CMOS process,”

Ming-Dou Ker, C.-Y. Lin, and T.-L. Chang

Proc. of 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 25-27, 2011, pp. 374-377.

81

“Design and implementation of capacitive sensor readout circuit on glass substrate for touch panel applications,”

T.-M. Wang and Ming-Dou Ker

Proc. of 2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 25-27, 2011, pp. 269-272.

82

“Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process,”

Ming-Dou Ker, C.-Y. Lin, and T.-L. Chang

Proc. of 2011 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, Apr. 10-14, 2011, pp. 717-718.

83

“On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance,”

C.-C. Yen, Ming-Dou Ker, W.-Y. Lin, C.-M. Yang, and T.-Y. Chen

Proc. of 13th International Conference on Electrostatics, Bangor, UK, Apr. 10-14, 2011.

84

“New transient detection circuit to detect ESD-induced disturbance for automatic recovery design in display panels,”

C.-C. Yen, W.-Y. Lin, Ming-Dou Ker, C.-M. Yang, S.-F. Chen, and T.-Y. Chen

Proc. of 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Athens, Greece, Apr. 6-8, 2011

85

“Modeling the parasitic capacitance of ESD protection SCR to co-design matching network in RF ICs,”

C.-Y. Lin and Ming-Dou Ker

Proc. of 2010 IEEE International Symposium on Next-Generation Electronics (ISNE), Kaohsiung, Taiwan, Nov. 18-19, 2010, pp. 104-107.

86

“Design of stimulus driver to suppress epileptic seizure with adaptive loading consideration,”

W.-L. Chen, C.-Y. Lin, and Ming-Dou Ker

Proc. of 2010 IEEE International Symposium on Next-Generation Electronics (ISNE), Kaohsiung, Taiwan, Nov. 18-19, 2010, pp. 9-12.

87

“Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process,”

Ming-Dou Ker, Y.-R. Wen, W.-Y. Chen, and C.-Y. Lin

Proc. of 2010 IEEE International Symposium on Next-Generation Electronics (ISNE), Kaohsiung, Taiwan, Nov. 18-19, 2010, pp. 100-103.

88

“On-chip ESD detection circuit for system-level ESD protection design,” (invited paper)

Ming-Dou Ker, W.-Y. Lin, C.-C. Yen, C.-M. Yang, T.-Y. Chen, and S.-F. Chen

Proc. of 2010 IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, China, Nov. 1-4, 2010, pp. 1584-1587.

89

“Dual SCR with low-and-constant parasitic capacitance for ESD protection in 5-GHz RF integrated circuits,”

C.-Y. Lin and Ming-Dou Ker

Proc. of 2010 IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, China, Nov. 1-4, 2010, pp. 707-709.

90

“Optimized layout on ESD protection diode with low parasitic capacitance,”

C.-T. Yeh and Ming-Dou Ker

Proc. of 2010 IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, China, Nov. 1-4, 2010, pp. 1701-1703.

91  

“On-chip solution in CMOS integrated circuits for system-level ESD protection,” (invited paper)

Ming-Dou Ker

Proc. of 2010 RCJ EOS/ESD/EMC Symposium, Tokyo, Japan, Oct. 21- 22, 2010, pp. 1-6.

92

“ESD protection design for low trigger voltage and high latch-up immunity,”

J.-C. Tseng, C.-T. Hsu, C.-K. Tsai, Y.-C. Liao, and Ming-Dou Ker

Proc. of 2010 IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 5-9, 2010, pp. 32-35.

93

“ESD protection design with lateral DMOS transistor in 40-V BCD technology,”

C.-T. Wang, Ming-Dou Ker, T.-H. Tang, and K.-C. Su

Proc. of 2010 IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 5-9, 2010, pp. 36-39.

94

“CDM ESD protection design with initial-on concept in nanoscale CMOS process,”

C.-Y. Lin and Ming-Dou Ker

Proc. of 2010 IEEE International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 5-9, 2010, pp. 193-196.

95

“On-panel readout circuit for capacitive sensor with LTPS technology,”

Y.-T. Lin, Y.-C. Lin, T.-M. Wang, and Ming-Dou Ker

Proc. of 2010 International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD), Tokyo, Japan, Jul. 5-7, 2010, pp. 121-124.

96

“Circuit design of stimulus driver for adaptive loading applications,”

Ming-Dou Ker, W.-L. Chen, C.-Y. Lin, and Y.-H. Weng

Proc. of 2010 Neural Interfaces Conference (NIC), Long Beach, USA, June 21-23, 2010, p. 125.

97  

“Close-loop epilepsy prosthesis devices with temporalspatial seizure detection and responsively therapeutic stimulation,”

C.-Y. Wu, J.-C. Chiou, Ming-Dou Ker, F.-Z. Shaw, S.-F. Liang, Y.-L. Hsin, L.-J. Lin, H.-M. Chiueh, and W.-T. Liu

Proc. of 2010 Neural Interfaces Conference (NIC), Long Beach, USA, June 21-23, 2010, p. 138.

98

“ESD protection design for differential low-noise amplifier with cross-coupled SCR,”

C.-Y. Lin, Ming-Dou Ker, and Y.-W. Hsiao

Proc. of 2010 IEEE International Conference on Integrated Circuit Design & Technology (ICICDT), Grenoble, France, Jun. 2-4, 2010, pp. 39-42.

99

“New transient detection circuit for electrical fast transient (EFT) protection design in display panels,”

Ming-Dou Ker, W.-Y. Lin, C.-C. Yen, C.-M. Yang, T.-Y. Chen, and S.-F. Chen

Proc. of 2010 IEEE International Conference on Integrated Circuit Design & Technology (ICICDT), Grenoble, France, Jun. 2-4, 2010, pp. 51-54.

100

“Design of charge pump circuit in low-voltage CMOS process with suppressed return-back leakage current,”

Y.-H. Weng, H.-W. Tsai, and Ming-Dou K

Proc. of 2010 IEEE International Conference on Integrated Circuit Design & Technology (ICICDT), Grenoble, France, Jun. 2-4, 2010, pp. 155-158.

101

“2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process,”

C.-Y. Lin and Ming-Dou Ker

Proc. of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, May 30-Jun. 2, 2010, pp. 3417-3420.

102

“ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup,”

Ming-Dou Ker, C.-L. Hsu, and W.-Y. Chen

Proc. of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, May 30-Jun. 2, 2010, pp. 989-992.

103

“Design of on-panel readout circuit for touch panel application,”

T.-M. Wang, Ming-Dou Ker, Y.-H. Li, C.-H. Kuo, C.-H. Li, Y.-J. Hsieh, and C.-T. Liu

Digest of 2010 SID International Symposium, Seminar, and Exhibition, Seattle, USA, May 23-28, 2010, pp. 1933-1936.

104

“Design of analog pixel memory circuit with low temperature polycrystalline silicon TFTs for low power application,”

L.-W. Chu, P.-T. Liu, Ming-Dou Ker, G.-T. Zheng, Y.-H. Li, C.-H. Kuo, C.-H. Li, Y.-J. Hsieh, and C.-T. Liu

Digest of 2010 SID International Symposium, Seminar, and Exhibition, Seattle, USA, May 23-28, 2010, pp. 1363-1366.

105

“Self-matched ESD cell in CMOS technology for 60-GHz broadband RF applications,”

C.-Y. Lin, L.-W. Chu, Ming-Dou Ker, T.-H. Lu, P.-F. Hung, and H.-C. Li

Proc. of 2010 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Anaheim, California, USA, May 23-25, 2010, pp. 573-576.

106

“A bending N-Well ballast layout to improve ESD robustness in fully-silicided CMOS technology,”

Y.-R. Wen, Ming-Dou Ker, and W.-Y. Chen

Proc. of 2010 IEEE International Reliability Physics Symposium (IRPS), Anaheim, California, USA, May 2-6, 2010, pp. 857-860.

107

“Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits,”

C.-T. Yeh, Y.-C. Liang, and Ming-Dou Ker

Proc. of 2010 International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Hsinchu, Taiwan, April 26-29, 2010, pp. 241-244.

108

“Protection design against system-level ESD transient disturbance on display panels,”

Ming-Dou Ker, W.-Y. Lin, C.-C. Yen, C.-M. Yang, T.-Y. Chen, and S.-F. Chen

Prof. of 2010 Asia-Pacific International Symposium on Electromagnetic Compatibility (APEMC), Beijing, China, April 12-16, 2010, pp. 445 - 448.

109

“Low-capacitance and low-loss bond pad design using LC-resonator structure in CMOS technology for RF and high-speed applications,”

C.-Y. Lin and Ming-Dou Ker

Prof. of 2009 International Conference on Solid Sate Devices and Materials (SSDM), Sendai, Miyagi, Japan, Oct. 6-9, 2009, pp. 372-373.

110

“Bi-directional SCR device with dual-triggered mechanism for ESD protection in extended-voltage-swing I/O application,”

Z.-W. Jiang, S.-H. Chen, and Ming-Dou Ker

Prof. of 2009 International Conference on Solid Sate Devices and Materials (SSDM), Sendai, Miyagi, Japan, Oct. 6-9, 2009, pp. 420-421.

111

“Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS,” (invited paper)

Ming-Dou Ker and C.-T. Wang

Prof. of 2009 IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, USA, Sep. 13-16, 2009, pp. 689-696.

112

Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices,

Ming-Dou Ker and Y.-L. Lin

Proc. of 2009 IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, Sep. 13-16, 2009, pp. 539-542.

113

“New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process,” 

Ming-Dou Ker, W.-Y. Chen, W.-T. Shieh, and I.-J. Wei

Proc. of 2009 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Anaheim, California, USA, Aug. 30-Sep.4, 2009, pp. 11-16.

114

“Transient-to-digital converter for protection design in CMOS integrated circuits against electrical fast transient,”

C.-C. Yen, Ming-Dou Ker, C.-S. Liao, T.-Y. Chen, and C.-C. Tsai,

Proc. of 2009 IEEE International Symposium on Electromagnetic Compatibility (EMC), Austin, Texas, USA, Aug. 17-21, 2009, pp. 41-44.

115

“Source-side engineering to increase holding voltage of LDMOS in a 0.5-μm 16-V BCD technology to avoid latch-up failure,

W.-Y. Chen, Ming-Dou Ker, Y.-N. Jou, Y.-J. Huang, and G.-L. Lin

Proc. of 2009 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Suzhou, China, Jul. 6-10, 2009, pp. 41-44.

116

“Chip-level and board-level CDM ESD tests on IC products,

Ming-Dou Ker, C.-K. Huang, Y.-W. Hsiao, and Y.-F. Hsieh

Proc. of 2009 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Suzhou, China, Jul. 6-10, 2009, pp. 45-49.

117

“On-panel analog output buffer with level shifting function in LTPS technology,

T.-M. Wang, S.-C. Chen, and Ming-Dou Ker

Proc. of 2009 International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD), Nara, Japan, Jul. 1-3, 2009, pp. 153-156.

118

“Design and realization of delta-sigma analog-to-digital converter in LTPS technology,

C.-C. Tsai, Ming-Dou Ker, Y.-H. Li, C.-H. Kuo, C.-H. Li, Y.-J. Hsieh, and C.-T. Liu

Proc. of 2009 International Symposium for Information Display (SID), San Antonio, Texas, USA, May 31-Jun. 5, 2009, pp. 1283-1286.

119

Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection,”

W.-Y. Chen, Ming-Dou Ker, Y.-N. Jou, Y.-J. Huang, and G.-L. Lin

Proc. of 2009 IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May 24-27, 2009, pp. 385-388.

120

On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process,”

Ming-Dou Ker, P.-Y. Chiu, F.-Y. Tsai, and Y.-J. Chang

Proc. of 2009 IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May 24-27, 2009, pp. 2281-2284.

121

Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology,” (invited paper)

C.-T. Wang, Ming-Dou Ker, T.-H. Tang, and K.-C. Su

Proc. of 2009 IEEE International Conference on Integrated Circuit Design & Technology (ICICDT), Austin, Texas, USA, May 18-20, 2009, pp. 21-24.

122

“Design of on-chip power-rail ESD clamp circuit with ultra-small capacitance to detect ESD transition,

S.-H. Chen and Ming-Dou Ker

Proc. of 2009 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 27-30, 2009, pp. 327-330.

123

“Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process,”

P.-Y. Chiu, Ming-Dou Ker, F.-Y. Tsai, and Y.-J. Chang

Proc. of 2009 IEEE International Reliability Physics Symposium (IRPS), Montreal, Canada, Apr. 26-30, 2009, pp. 750-753.

124

“Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration,”

W.-Y. Chen, Ming-Dou Ker, Y.-J. Huang, Y.-N. Jou, and G.-L. Lin

Proc. of 2008 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), Macao, China, Nov. 30-Dec. 3, 2008, pp. 61-64.

125

“Transient-to-digital converter for ESD protection design in microelectronic systems,”

Ming-Dou Ker, C.-C. Yen, C.-S. Liao, T.-Y. Chen, and C.-C. Tsai

Proc. of 2008 Asian Solid-State Circuits Conference (A-SSCC), Fukuoka, Japan, Nov. 3-5, 2008, pp. 409-412.

126

“An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process,

Y.-W. Hsiao and Ming-Dou Ker

Proc. of 2008 IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, Sep. 21-24, 2008, pp. 233-236.

127

“Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-um LTPS process,

T.-C. Lu, Ming-Dou Ker, H.-W. Zan, C.-H. Kuo, C.-H. Li, Y.-J. Hsieh, and C.-T. Liu

Proc. of 2008 IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, Sep. 21-24, 2008, pp. 721-724.

128

“CDM ESD protection in CMOS integrated circuits,”

Ming-Dou Ker and Y.-W. Hsiao

Proc. of Argentine Conference of Micro-Nanoelectronics, Technology and Applications (EAMTA), Buenos Aires, Argentina, Sep. 13-22, 2008, pp. 61-66.

129

On-glass digital-to-analog converter with gamma correction for panel data driver,”

T.-M. Wang, Y.-H. Li, and Ming-Dou Ker

Proc. of the 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Malta, Aug. 31-Sep. 3, 2008, pp. 202-205.

130

Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology,”

S.-H. Chen and Ming-Dou Ker

Proc. of the 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Malta, Aug. 31-Sep. 3, 2008, pp. 666-669.

131

Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process,”

Ming-Dou Ker, T.-M. Wang, and F.-L. Hu

Proc. of the 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Malta, Aug. 31-Sep. 3, 2008, pp. 1047-1050.

132

“Transient detection circuit for system-level ESD protection and its on-board behavior with EMI/EMC filters,

Ming-Dou Ker, C.-S. Liao, and C.-C. Yen

Proc. of 2008 IEEE International Symposium on Electromagnetic Compatibility (EMC), Detroit, Michigan, USA, Aug. 18-22, 2008.

133

“Co-design strategy with low-C consideration for on-chip ESD protection in RF ICs,

C.-Y. Lin and Ming-Dou Ker

Proc. of International PhD Student Workshop on SOC (IPS), Kenting, Taiwan, Aug. 3-7, 2008.

134

“Design of analog circuits on glass substrate,

T.-M. Wang and Ming-Dou Ker

Proc. of International PhD Student Workshop on SOC (IPS), Kenting, Taiwan, Aug. 3-7, 2008.

135

“Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits,

C.-Y. Lin and Ming-Dou Ker

Proc. of 2008 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 7-11, 2008, pp. 58-61.

136

“On-glass bandgap voltage reference circuit in a 3-μm LTPS process,

T.-C. Lu, Ming-Dou Ker, H.-W. Zan, C.-H. Kuo, C.-H. Li, Y.-J. Hsieh, and C.-T. Liu

Proc. of 2008 International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD), Tokyo, Japan, Jul. 2-4, 2008, pp. 201-204.

137

“Design of on-panel digital-to-analog converter with reordering decoder circuit in LTPS technology,

T.-M. Wang, Y.-H. Li, and Ming-Dou Ker

Proc. of 2008 International Workshop on Active-Matrix Flatpanel Displays and Devices (AM-FPD), Tokyo, Japan, Jul. 2-4, 2008, pp. 221-224.

138

“Temperature coefficient of diode-connected LTPS poly-Si TFTs and its application on the bandgap reference circuit,

T.-C. Lu, H.-W. Zan, Ming-Dou Ker, W.-M. Huang, K.-C. Lin, C.-C. Shih, C.-C. Chiu, and C.-T. Liu

Proc. of 2008 International Symposium for Information Display (SID), Los Angeles, California, USA, May 18-23, 2008, pp. 1410-1413.

139

2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue,”

Ming-Dou Ker, T.-M. Wang, and H.-T. Liao

Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, USA, May 18-21, 2008, pp. 820-823.

140

“ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR,”

Ming-Dou Ker, C.-Y. Lin, and G.-X. Meng

Proc. of 2008 IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, USA, May 18-21, 2008, pp. 1292-1295.

141

Investigation on discharge current waveforms in board-level CDM ESD events with different board sizes,

Y.-W. Hsiao and Ming-Dou Ker

Presentations of the 2nd International ESD Workshop (IEW), Port D’Albret, France, May 12-15, 2008, pp. 284-296.

142

The impact of BIGFET clamp device layout on ESD protection circuit robustness,

C.-T. Yeh, Y.-C. Liang, and Ming-Dou Ker

Presentations of the 2nd International ESD Workshop (IEW), Port D’Albret, France, May 12-15, 2008, pp. 414-425.

143

Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits,”

J.-C. Tseng, Y.-L. Chen, C.-T. Hsu, F.-Y. Tsai, P.-A. Chen, Ming-Dou Ker

Proc. of 2008 IEEE International Reliability Physics Symposium (IRPS), Phoenix, Arizona, USA, Apr. 27-May 1, 2008, pp. 625-626.

144

High-robust ESD protection structure with embedded SCR in high-voltage CMOS process,”

T.-H. Lai, Ming-Dou Ker, W.-J. Chang, T.-H. Tang, and K.-C. Su

Proc. of 2008 IEEE International Reliability Physics Symposium (IRPS), Phoenix, Arizona, USA, Apr. 27-May 1, 2008, pp. 627-628.

145

“New transient detection circuit for system-level ESD protection,

C.-C. Yen, C.-S. Liao, and Ming-Dou Ker

Proc. of 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 23-25, 2008, pp. 180-183.

146

ESD protection design for RF circuits in CMOS technology with low-C implementation,” (invited paper)

C.-Y. Lin and Ming-Dou Ker

Proc. of the 7th International Semiconductor Technology Conference (ISTC 2008), Shanghai, China, Mar. 15-17, 2008, pp. 70-75.

147

A new architecture for charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes,”

T.-M. Wang, W.-Y. Shen, and Ming-Dou Ker

Proc. of the 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco, Dec. 11-14, 2007, pp. 206-209.

148

CMOS power amplifier with ESD protection design merged in matching network,”

Y.-D. Shiu, B.-S Huang, and Ming-Dou Ker

Proc. of the 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco, Dec. 11-14, 2007, pp. 825-828.

149

Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation,”

H.-W. Tsai and Ming-Dou Ker

Proc. of the 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2007), Marrakech, Morocco, Dec. 11-14, 2007, pp. 1240-1243.

150

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits,”

S.-H. Chen and Ming-Dou Ker

Proc. of the 18th European Symposium on Reliability of Electron Devices (ESREF), Bordeaux, France, Oct. 8-12, 2007, pp. 1502-1505. (also in the Special Issue in Microelectronics Reliability, vol. 47, no. 9-11, pp. 1502-1505, Sep.-Nov. 2007).

151

ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process,”

Y.-W. Hsiao, Ming-Dou Ker, P.-Y. Chiu, C. Huang, and Y.-K. Tseng

Proc. of 2007 IEEE International SOC Conference, Hsinchu, Taiwan, Sep. 26-29, 2007, pp. 277-280.

152

Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution,”

Ming-Dou Ker and C.-C. Yen

Proc. of 18th International Zurich Symposium on Electromagnetic Compatibility (EMC-Zurich), Munich, Germany, Sep. 24-28, 2007, pp. 69-72.

153

Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology,”

S.-H. Chen and Ming-Dou Ker

Proc. of 2007 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Bangalore, India, Jul. 11-13, 2007, pp. 245-248.

154

The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process,”

W.-J. Chang, Ming-Dou Ker, T.-X. Lai, T.-H. Tang, and K.-C. Su

Proc. of 2007 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Bangalore, India, Jul. 11-13, 2007, pp. 249-252.

155

Transient-induced latchup in CMOS integrated circuits due to electrical fast transient (EFT) test,”

C.-C. Yen and Ming-Dou Ker

Proc. of 2007 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Bangalore, India, Jul. 11-13, 2007, pp. 253-256.

156

Latchup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test,

Ming-Dou Ker and C.-C. Yen

Proc. of 2007 IEEE International Symposium on Electromagnetic Compatibility (EMC), Honolulu, Hawaii, USA, Jul. 8-13, 2007.

157

Ultra low-capacitance bond pad for RF applications in CMOS technology,

Y.-W. Hsiao and Ming-Dou Ker

Proc. of 2007 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, Hawaii, USA, Jun. 3-5, 2007, pp. 303-306.

158

Low-capacitance SCR with waffle layout structure for on-chip ESD Protection in RF ICs,

C.-Y. Lin and Ming-Dou Ker

Proc. of 2007 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Honolulu, Hawaii, USA, Jun. 3-5, 2007, pp. 749-752.

159

Design of mixed-voltage crystal oscillator circuit in low-voltage CMOS technology,

Ming-Dou Ker and H.-T. Liao

Proc. of 2007 IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, May 27-30, 2007, pp. 1121-1124.

160

Investigation on ESD robustness of P-type TFTs under different layout structures in LTPS process for on-panel ESD protection design,

Ming-Dou Ker, J.-Y. Chuang, C.-K. Deng, C.-H. Li, and C.-H. Kuo

Presentations of the 1st International ESD Workshop (IEW), South Lake Tahoe, California, USA, May 14-17, 2007, pp. 228-239.

161

“Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability,

Ming-Dou Ker and F.-L. Hu

Proc. of 2007 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 25-27, 2007, pp. 36-39.

162

“Automation of synchronous bias transmission line pulsing system,

B.-W. Chang, H.-C. Hsu, and Ming-Dou Ker

Proc. of 2007 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 25-27, 2007, pp. 232-235.

163

“Board level ESD of driver ICs on LCD panels,”

C.-T. Hsu, J.-C. Tseng, Y.-L. Chen, F.-Y. Tsai, S.-H. Yu, P.-A. Chen, and Ming-Dou Ker

Proc. of 2007 IEEE International Reliability Physics Symposium (IRPS), Phoenix, Arizona, USA, Apr. 15-19, 2007, pp. 590-591.

164

Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes,”

Ming-Dou Ker, C.-T. Wang, T.-H. Tang, and K.-C. Su

Proc. of 2007 IEEE International Reliability Physics Symposium (IRPS), Phoenix, Arizona, USA, Apr. 15-19, 2007, pp. 594-595.

165

“Failure of on-chip power-rail ESD clamp circuits during system-level ESD test,”

C.-C. Yen and Ming-Dou Ker

Proc. of 2007 IEEE International Reliability Physics Symposium (IRPS), Phoenix, Arizona, USA, Apr. 15-19, 2007, pp. 598-599.

166

“Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology,”

J.-S. Chen and Ming-Dou Ker

Proc. of 2007 IEEE International Reliability Physics Symposium (IRPS), Phoenix, Arizona, USA, Apr. 15-19, 2007, pp. 664-665.

167

“Test structure on SCR device in waffle layout for RF ESD protection,”

Ming-Dou Ker and C.-Y. Lin

Proc. of 2007 IEEE International Conf. on Microelectronics Test Structures (ICMTS), Tokyo, Japan, Mar. 19-22, 2007, pp. 196-199.

168

On-panel analog output buffer for data driver with consideration of device characteristic variation in LTPS technology,”

Y.-H. Li, Ming-Dou Ker, C.-Y. Huang, and C.-Y. Hsu

Proc. of Asia Display 2007, Shanghai, China, Mar. 12-16, 2007, pp. 210-215.

169

On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process,”

Ming-Dou Ker, J.-Y. Chuang, C.-K. Deng, C.-H. Kuo, C.-H. Li, M.-S. Lai, C.-W. Wang, and C.-T. Liu

Proc. of Asia Display 2007, Shanghai, China, Mar. 12-16, 2007, pp. 551-556.

170

“Low-power wordline voltage generator for low-voltage flash memory,”

T.-M. Wang, Ming-Dou Ker, S. Yeh., and Y.-C. Chang

Proc. of the 13th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2006), Nice, France, Dec. 10-13, 2006, pp. 220-223.

171

“System-level ESD protection design with on-chip transient detection circuit,”

C.-C. Yen, Ming-Dou Ker, and P.-C. Shih

Proc. of the 13th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2006), Nice, France, Dec. 10-13, 2006, pp. 616-619.

172

“ESD protection design by using only 1xVDD low-voltage devices for mixed-voltage I/O buffers with 3xVDD input tolerance,”

Ming-Dou Ker and C.-T. Wang

Proc. of 2006 Asian Solid-State Circuits Conference (A-SSCC), Hangzhou, China, Nov. 13-15, 2006, pp. 287-290.

173

“On-chip ESD protection strategies for RF circuits in CMOS technology,” (invited paper)

Ming-Dou Ker and Y.-W. Hsiao

Proc. of the 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Shanghai, China, Oct. 23-26, 2006, pp. 1680-1683.

174

“ESD robustness of 40-V CMOS devices with/without drift implantation,”

W.-J. Chang, Ming-Dou Ker, T.-X. Lai, T.-H. Tang, and K.-C. Su

Proc. of 2006 IEEE International Integrated Reliability Workshop (IRW), Lake Tahoe, USA, Oct. 16-19, 2006, pp. 167-170.

175

“Optimization on layout structures of LTPS TFTs for on-panel ESD protection design,”

C.-K. Deng, Ming-Dou Ker, J.-Y. Chung, and W.-T. Sun

Proc. of 2006 International Conference on Solid State Devices and Materials (SSDM), Yokohama, Japan, Sep. 12-15, 2006, pp. 600-601.

176

On-chip transient detection circuit for system-level ESD protection in CMOS ICs,

Ming-Dou Ker, C.-C. Yen, and P.-C. Shih

Proc. of 2006 IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, Sep. 10-13, 2006, pp. 361-364.

177

Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS process,”

J.-S. Chen and Ming-Dou Ker

Proc. of 2006 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 3-7, 2006, pp. 45-48.

178

Abnormal ESD damages occur in interface circuits between different power domains in ND-mode MM ESD stress,”

H.-P. Hung, Ming-Dou Ker, S.-H. Chen, and C.-H. Chuang

Proc. of 2006 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 3-7, 2006, pp. 163-166.

179

ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces,

W.-J. Chang and Ming-Dou Ker

Proc. of the 2nd Conference on Ph.D. Research in MicroElectronics and Electronics, Otranto (Lecce), Italy, Jun. 12-15, 2006, pp. 305-308.

180

“Design on new tracking circuit of I/O buffer in 0.13-µm cell library of mixed-voltage application,

Z.-P. Chen, C.-H. Chuang, and Ming-Dou Ker

Proc. of 2006 IEEE International Symposium on Circuits and Systems (ISCAS), Island of Kos, Greece, May 21-24, 2006, pp. 2213-2216.

181

“New matching methodology of low-noise amplifier with ESD protection,

B.-S. Huang and Ming-Dou Ker

Proc. of 2006 IEEE International Symposium on Circuits and Systems (ISCAS), Island of Kos, Greece, May 21-24, 2006, pp. 4891-4894.

182

“Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications,

Ming-Dou Ker and C.-H. Wu

Proc. of 2006 IEEE International Symposium on Circuits and Systems (ISCAS), Island of Kos, Greece, May 21-24, 2006, pp. 5155-5158.

183

Investigation on RF characteristics of stacked P-I-N polyslilcon diodes for ESD protection design in 0.18-μm CMOS technology,

Y.-D. Shiu, C.-H. Chuang, and Ming-Dou Ker

Proc. of 2006 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 24-26, 2006, pp. 56-57.

184

Experimental evaluation and device simulation of device structure influences on latch up immunity in high-voltage 40-V CMOS process,”

S.-F. Hsu, Ming-Dou Ker, G.-L. Lin, and Y.-N. Jou

Proc. of 2006 IEEE International Reliability Physics Symposium (IRPS), San Jose, California, USA, Mar. 26-30, 2006, pp. 140-144.

185

“The impact of inner pickup on ESD robustness of multi-finger NMOS in nanoscale CMOS technology,”

Ming-Dou Ker and H.-C. Hsu

Proc. of 2006 IEEE International Reliability Physics Symposium (IRPS), San Jose, California, USA, Mar. 26-30, 2006, pp. 631-632.

186

“Dependence of layout parameters on CDE (cable discharge event) robustness of CMOS devices in a 0.25-µm salicided CMOS process,”

Ming-Dou Ker and T.-X. Lai

Proc. of 2006 IEEE International Reliability Physics Symposium (IRPS), San Jose, California, USA, Mar. 26-30, 2006, pp. 633-634.

187

“Circuit performance degradation of sample-and-hold amplifier due to gate-oxide overstress in a 130-nm CMOS process,”

J.-S. Chen and Ming-Dou Ker

Proc. of 2006 IEEE International Reliability Physics Symposium (IRPS), San Jose, California, USA, Mar. 26-30, 2006, pp. 705-706.

188

Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask,”

H.-C. Hsu and Ming-Dou Ker

Proc. of 2006 IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, Mar. 27-29, 2006, pp. 503-506.

189

Method to evaluate cable discharge event (CDE) reliability of integrated circuits in CMOS technology,”

T.-X. Lai and Ming-Dou Ker

Proc. of 2006 IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, Mar. 27-29, 2006, pp. 597-602.

190

Study of board-level noise filters to prevent transient-induced latchup in CMOS integrated circuits during EMC/ESD test,”

S.-F. Hsu and Ming-Dou Ker

Proc. of 17th International Zurich Symposium on Electromagnetic Compatibility (EMC-Zurich), Singapore, Feb. 28-Mar. 3, 2006, pp. 533-536.

191

“ESD protection for mixed-voltage I/O in low-voltage thin-oxide CMOS,” 

Ming-Dou Ker, W.-J. Chang, C.-T. Wang, and W.-Y. Chen

Technical Digest of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 5-9, 2006, pp. 546-547.

192

ESD protection design for mixed-voltage I/O interfaces-overview,” (invited paper)

Ming-Dou Ker and K.-H. Lin

Proc. of 2005 IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Dec. 19-21, 2005, pp. 493-498.

193

Methodology to evaluate the robustness of integrated circuits under cable discharge event,”

T.-X. Lai and Ming-Dou Ker

Proc. of 2005 IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Dec. 19-21, 2005, pp. 499-502.

194

“Initial-on ESD protection design with PMOS-triggered SCR device,” 

Ming-Dou Ker and S.-H. Chen

Proc. of 2005 Asian Solid-State Circuits Conference (A-SSCC), Hsinchu, Taiwan, Nov. 1-3, 2005, pp. 105-108.

195

“On-chip high-voltage charge pump circuit in standard CMOS processes with polysilicon diode,” 

Ming-Dou Ker and S.-L. Chen

Proc. of 2005 Asian Solid-State Circuits Conference (A-SSCC), Hsinchu, Taiwan, Nov. 1-3, 2005, pp. 157-160.

196

Investigation on seal-ring rules for IC product reliability in 0.25-µm CMOS technology,”

S.-H. Chen and Ming-Dou Ker

Proc. of the 16th European Symposium on Reliability of Electron Devices (ESREF), Bordeaux, France, Oct. 10-14, 2005, pp. 1311-1316. (also in the Special Issue in Microelectronics Reliability, vol. 45, no. 9-11, pp. 1311-1316, Sep.-Nov. 2005).

197

“ESD protection design with the low-leakage-current diode string for RF circuits in BiCMOS SiGe process,” 

Ming-Dou Ker and W.-L. Wu

Proc. of 2005 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Anaheim, USA, Sep. 12-14, 2005, pp. 18-24.

198

“Dependences of damping frequency and damping factor of bi-polar trigger waveforms on transient-induced latchup,” 

S.-F. Hsu and Ming-Dou Ker

Proc. of 2005 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Anaheim, USA, Sep. 12-14, 2005, pp. 118-125.

199

“Evaluation on board-level noise filter networks to suppress transient-induced latchup under system-level ESD test,” 

Ming-Dou Ker and S.-F. Hsu

Proc. of 2005 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Anaheim, USA, Sep. 12-14, 2005, pp. 262-269.

200

ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications,

Ming-Dou Ker, W.-J. Chang, M. Yang, C.-C. Chen, M.-C. Chan, W.-T. Shieh, and K.-L. Yen

Proc. of 2005 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jun. 27-Jul. 1, 2005, pp. 67-70.

201

A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology,

S.-H. Chen, Ming-Dou Ker, and C.-H. Chuang

Proc. of 2005 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jun. 27-Jul. 1, 2005, pp. 209-212.

202

On-panel design technique of threshold voltage compensation for output buffer in LTPS technology,

Ming-Dou Ker, C.-K. Deng, and J.-L. Huang

Proc. of 2005 International Symposium for Information Display (SID), Boston, Massachusetts, USA, May 22-27, 2005, pp. 288-291.

203

“ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure,

K.-H. Lin and Ming-Dou Ker

Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 23-26, 2005, pp. 1182-1185.

204

“Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications,

Ming-Dou Ker, S.-L. Chen, and C.-S. Tsai

Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 23-26, 2005, pp. 1859-1862.

205

“New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation,

Ming-Dou Ker, J.-S. Chen, and C.-Y. Chu

Proc. of 2005 IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, May 23-26, 2005, pp. 3861-3864.

206

“Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices,

Ming-Dou Ker, J.-H. Chen, and K.-C. Hsu

Proc. of 2005 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 25-27, 2005, pp. 17-18.

207

“Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology,

H.-C. Hsu, C.-M. Chen, and Ming-Dou Ker

Proc. of 2005 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 25-27, 2005, pp. 19-20.

208

“Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger,”

Ming-Dou Ker and S.-F. Hsu

Proc. of 2005 IEEE International Reliability Physics Symposium (IRPS), San Jose, California, USA, Apr. 17-21, 2005, pp. 121-128.

209

“Impact of MOSFET gate-oxide reliability on CMOS operational amplifiers in a 130-nm low-voltage CMOS process,”

J.-S. Chen and Ming-Dou Ker

Proc. of 2005 IEEE International Reliability Physics Symposium (IRPS), San Jose, California, USA, Apr. 17-21, 2005, pp. 423-430.

210

“Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process,”

Ming-Dou Ker, W.-Y. Chen, and K.-C. Hsu

Proc. of 2005 IEEE International Reliability Physics Symposium (IRPS), San Jose, California, USA, Apr. 17-21, 2005, pp. 606-607.

211

“Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3xVDD input tolerance by using 1xVDD devices and single VDD power supply,”

Ming-Dou Ker and S.-L. Chen

Technical Digest of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 6-10, 2005, pp. 524-525.

212

 

“Failure analysis and solutions to overcome latchup event of a power controller IC product,”

S.-H. Chen, Ming-Dou Ker, and C.-P. Weng

Proc. of 2004 International Electron Devices and Materials Symposia, Hsinchu, Taiwan, Dec. 20-23, 2004, pp. 323-326.

213

“Transient-induced latchup in CMOS technology: physical mechanism and device simulation,”

Ming-Dou Ker and S.-F. Hsu

Technical Digest of IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Dec. 13-15, 2004, pp. 937-940.

214

“Co-design on broadband CMOS RF distributed amplifier with on-chip ESD protection circuit,” (invited paper)

Ming-Dou Ker, B.-J. Kuo, and Y.-W. Hsiao

Abstracts of the 16th Asia Pacific Microwave Conference (APMC), New Delhi, India, Dec. 15-18, 2004, p. 7.

215

Circuit design to achieve whole-chip ESD protection for UXGA/HDTV LCoS IC product,”

Ming-Dou Ker, S.-H. Chen, and T.-K. Tseng

Proc. of 2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004), Tainan, Taiwan, Dec. 6-9, 2004, pp. 845-848.

216

“New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology,”

Ming-Dou Ker and K.-C. Hsu

Proc. of 2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004), Tainan, Taiwan, Dec. 6-9, 2004, pp. 841-844.

217  

“Active ESD shunt with transistor feedback to reduce latchup susceptibility or false triggering,”

P. Tong, W. Chen, Ming-Dou Ker, J. Hui, P.-P. Xu, and P. Liu

Proc. of the 7th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Beijing, China, Oct. 18-21, 2004, pp. 820-823.

218  

“NMOS with dummy-gate structure to improve machine-model ESD robustness in a fully-salicided CMOS technology,”

H.-C. Hsu, C.-M. Chen, and Ming-Dou Ker

Proc. of 2004 International Conference on Electromagnetic Applications and Compatibility (ICEMAC), Taipei, Taiwan, Oct. 14-15, 2004.

219  

“Degradation of LTPS thin-film transistors during continue ESD stress by transmission line pulses,”

C.-K. Deng, Ming-Dou Ker, S.-C. Yang, and Y.-M. Tasi

Proc. of 2004 International Conference on Electromagnetic Applications and Compatibility (ICEMAC), Taipei, Taiwan, Oct. 14-15, 2004.

220  

“Design on analog I/O cell in 0.18-µm CMOS technology,”

S.-H. Chen, Ming-Dou Ker, C.-H. Chuang, and Z.-P. Chen

Proc. of 2004 International Conference on Electromagnetic Applications and Compatibility (ICEMAC), Taipei, Taiwan, Oct. 14-15, 2004.

221

Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme,” 

Ming-Dou Ker and B.-J. Kuo

Proc. of 2004 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Grapevine, Texas, USA, Sep. 19-23, 2004, pp. 32-39.

222

Latchup test-induced failure within ESD protection diodes in a high-voltage CMOS IC product,”

I-C. Lin, C.-J. Chao, Ming-Dou Ker, J.-C. Tsen, C.-T. Hsu, L.-Y. Leu, Y.-L. Chen, C.-K. Tsai and R.-W. Huang

Proc. of 2004 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Grapevine, Texas, USA, Sep. 19-23, 2004, pp. 160-165.

223

Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs,”

K.-H. Lin and Ming-Dou Ker

Proc. of 2004 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Grapevine, Texas, USA, Sep. 19-23, 2004, pp. 265-272.

224

“A new output buffer for 3.3-V PCI-X application in a 0.13-µm 1/2.5-V CMOS process,

S.-L. Chen and Ming-Dou Ker

Proc. of the 4th IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC 2004), Fukuoka, Japan, Aug. 4-5, 2004, pp. 112-115.

225

Correlation between transmission-line pulsing I-V curve and human-body-model ESD level on low temperature poly-si TFT devices,”

Ming-Dou Ker, C.-L. Hou, C.-Y. Chang, and F.-T. Chu

Proc. of 2004 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Taiwan, Jul. 5-8, 2004, pp. 209-212.

226

Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces,”

W.-J. Chang and Ming-Dou Ker

Proc. of 2004 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Taiwan, Jul. 5-8, 2004, pp. 213-216.

227

ESD protection design for high-speed I/O interfaces of stub series terminated logic (SSTL) in a 0.25-µm salicided CMOS process,”

Ming-Dou Ker and C.-H. Chuang

Proc. of 2004 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Taiwan, Jul. 5-8, 2004, pp. 217-220.

228  

Design strategy on electrostatic discharge (ESD) protection for nano-scale CMOS integrated circuits,” (invited paper)

Ming-Dou Ker

Proc. of 2004 Taiwan International Conference on Nano Science and Technology (TICON), Hsinchu, Taiwan, Jun. 30-Jul. 3, 2004, pp. 132-137.

229

ESD protection for broadband RF circuits with decreasing-size distributed protection scheme,

Ming-Dou Ker and B.-J. Kuo

Proc. of 2004 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Fort Worth, Texas, USA, Jun. 6-8, 2004, pp. 383-386.

230

“On-chip ESD protection design for UXGA/HDTV LCoS in 0.35-µm CMOS technology,”

 Ming-Dou Ker, S.-H. Chen, and T.-K. Tseng

Proc. of 2004 International Symposium for Information Display (SID), Seattle, Washington, USA, May 23-28, 2004, pp. 404-407.

231

“ESD protection design for IC with power-down-mode operation,”

Ming-Dou Ker and K.-H. Lin

Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, May 23-26, 2004, vol. 2, pp. 717-720.

232

“Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology,”

C.-H. Chuang and Ming-Dou Ker

Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, May 23-26, 2004, vol.2, pp. 577-580.

233

“A new Schmitt trigger circuit in a 0.13-µm 1V/2.5V CMOS process to receive 3.3-V input signals,”

S.-L. Chen and Ming-Dou Ker

Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, May 23-26, 2004, vol. 2, pp. 573-576.

234

“A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes,”

 Ming-Dou Ker, S.-L. Chen, and C.-S. Tsai

Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, May 23-26, 2004, vol. 1, pp. 321-325.

235

“A CMOS bandgap reference circuit for sub-1-V operation without using extra low threshold-voltage device,”

Ming-Dou Ker, J.-S. Chen, and C.-Y. Chu

Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), Vancouver, Canada, May 23-26, 2004, vol. 1, pp. 41-44.

236

“Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-µm CMOS integrated circuits,”

Ming-Dou Ker and K.-C. Hsu

Proc. of 2004 IEEE International Reliability Physics Symposium (IRPS), Phoenix, Arizona, USA, Apr. 25-29, 2004, pp. 381-386.

237

 “ Low-voltage-triggered PNP devices for ESD protection design in the mixed-voltage I/O interface with over-VDD and under-VSS signal levels,”

Ming-Dou Ker, W.-J. Chang, and W.-Y. Lo

Proc. of 2004 IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, Mar. 22-24, 2004, pp. 433-438.

238

“Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes,”

Ming-Dou Ker and W.-Y. Chen

Proc. of 2004 IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, Mar. 22-24, 2004, pp. 445-450.

239

“Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process,”

Ming-Dou Ker, W.-L. Wu, and C.-Y. Chang

Proc. of 2004 IEEE International Conf. on Microelectronics Test Structures (ICMTS), Awaji Yumebutai, Hyogo, Japan, Mar. 22-25, 2004, pp. 7-12.

240

“Test structure to verify ESD robustness of on-glass devices in LTPS technology,”

Ming-Dou Ker, C.-K. Deng, S.-C. Yang, and Y.-M. Tasi

Proc. of 2004 IEEE International Conf. on Microelectronics Test Structures (ICMTS), Awaji Yumebutai, Hyogo, Japan, Mar. 22-25, 2004, pp. 13-17.

241  

ESD protection scheme for I/O interface of CMOS IC operating in the power-down mode on system board,

K.-H. Lin and Ming-Dou Ker

Proc. of the 4th WSEAS International Conf. on Nanoelectronics and Nanotechnology (ICONN 2004), Kenting, Taiwan, Jan. 14-16, 2004, pp. 1561-1567.

242  

Double-triggered SCR with enhanced turn-on speed for effective ESD protection in nano-scale CMOS technology,

Ming-Dou Ker, K.-C. Hsu, and H.-C. Hsu

Proc. of the 4th WSEAS International Conf. on Nanoelectronics and Nanotechnology (ICONN 2004), Kenting, Taiwan, Jan. 14-16, 2004, pp. 1571-1575.

243

ASIC with Interpolator for Incremental Optical Encoders,”

C.-J. Yang, C.-F. Kao, Y.-Y. Chen, C.-F. Lin, T.-L. Chen and Ming-Dou Ker

Proc. of the 7th International Conference on Mechatronics Technology (ICMT), Taipei, Taiwan, Dec. 2-6, 2003, pp. 713-718.

244

“A high-efficient level shifter using active body-bias technique for LCD driver in LTPS technology,”

Ming-Dou Ker, W.-J. Hsu, Y.-H. Li, A. Shih, and Y.-M. Tasi

Proc. of the 10th International Display Workshops (IDW), Fukuoka, Japan, Dec. 3-5, 2003, pp. 371-374.

245

“Degradation of LTPS-TFT devices caused by electrostatic discharge,”

Ming-Dou Ker, C.-K. Deng, T.-K. Tseng, S.-C. Yang, A. Shih, and Y.-M. Tasi

Proc. of the 10th International Display Workshops (IDW), Fukuoka, Japan, Dec. 3-5, 2003, pp. 407-410.

246  

“Analysis and prevention on NC-ball induced ESD damages in a 683-pin BGA packaged chipset IC,”

W.-Y. Lo and Ming-Dou Ker

Proc. of the 14th European Symposium on Reliability of Electron Devices (ESREF), Arcachon, France, Oct. 7-10, 2003, pp. 1583-1588. (also in the Special Issue in Microelectronics Reliability, vol. 43, no. 9-11, pp. 1583-1588, Sep.-Nov. 2003).

247

“ESD protection design for Giga-Hz RF CMOS LNA with novel impedance-isolation technique,”

Ming-Dou Ker and C.-M. Lee

Proc. of 2003 Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Las Vegas, Nevada, USA, Sep. 21-25, 2003, pp. 204-213.

248

“ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique,”

Ming-Dou Ker and H.-C. Hsu

Proc. of 2003 IEEE International SOC Conference, Portland, OR. USA, Sep. 17-20, 2003, pp. 219-222.

249

“Novel ESD protection design for nanoscale CMOS integrated circuits,”

Ming-Dou Ker and T.-K. Tseng

Proc. of 2003 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan Sep. 16-18, 2003, pp. 426-427.

250

“Low-voltage-triggered PNP for ESD protection in mixed-voltage I/O interface,”

Ming-Dou Ker, W.-J. Chang, and W.-Y. Lo

Proc. of 2003 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan Sep. 16-18, 2003, pp. 404-405.

251

“Improvement on turn-on speed of substrate-triggered SCR device by using dummy-gate structure for on-chip ESD protection,”

K.-C. Hsu and Ming-Dou Ker

Proc. of 2003 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan Sep. 16-18, 2003, pp. 440-441.

252

“Dynamic holding voltage SCR (DHVSCR) device for ESD protection with high latch-up immunity,”

Z.-P. Chen and Ming-Dou Ker

Proc. of 2003 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan Sep. 16-18, 2003, pp. 160-161.

253

Novel electrostatic discharge protection design for nanoelectronics in nanoscale CMOS technology,”

Ming-Dou Ker and T.-K. Tseng

Proc. of the 3rd IEEE Conference on Nanotechnology (IEEE-Nano), San Francisco, CA., USA, Aug. 12-14, 2003, pp. 737-740.

254

“Analysis of abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing non-connected balls,”

W.-Y. Lo and Ming-Dou Ker

Proc. of 2003 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 7-11, 2003, pp. 174-178.

255

“Design on LTPS p-i-n diode and its application for whole-panel electrostatic discharge protection,”

S.-C. Yang, Ming-Dou Ker, T.-K. Tseng, A. Shih, and Y.-M. Tsai

Proc. of 2003 International Workshop on Active-Matrix Liquid-Crystal Displays (AM-LCD), Tokyo, Japan, Jul. 9-11, 2003, pp. 321-324.

256

“High ESD robust TFT devices with source-side body contacts for I/O application,”

Ming-Dou Ker, C.-K. Deng, T.-K. Tseng, S.-C. Yang, A. Shih, and Y.-M. Tsai

Proc. of 2003 International Workshop on Active-Matrix Liquid-Crystal Displays (AM-LCD), Tokyo, Japan, July 9-11, 2003, pp. 165-168.

257

“A novel LC-tank ESD protection design for giga-Hz RF circuits,”

Ming-Dou Ker, C.-I. Chou, and C.-M. Lee

Proc. of 2003 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Philadelphia, Pennsylvania, USA, Jun. 8-10, 2003, pp. 115-118.

258

“Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic n-well bias circuit,”

Ming-Dou Ker and C.-S. Tsai

Proc. of 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, May 25-28, 2003, vol. 5, pp. 97-100.

259

“Interference of ESD protection diodes on RF performance in giga-Hz RF circuits,”

Ming-Dou Ker and C.-M. Lee

Proc. of 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, May 25-28, 2003, vol. 1, pp. 297-300.

260

“Successful electrostatic discharge protection design for LTPS circuits integrated on panel,”

Ming-Dou Ker, T.-K. Tseng, A. Shin, S.-C. Yang, and Y.-M. Tsai

Proc. of 2003 International Symposium for Information Display (SID), Baltimore, Maryland, USA, May 18-23, 2003, pp. 1400-1403.

261

“MOS-bounded diodes for on-chip ESD protection in a 0.15-µm shallow-trench-isolation salicided CMOS process,”

Ming-Dou Ker, K.-H. Lin, and C.-H. Chuang

Proc. of 2003 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taiwan, Apr. 23-25, 2003, pp. 84-87.

262

“Evaluation on ESD robustness of LTPS diode and TFT device by transmission line pulsing (TLP) technique,”

T.-K. Tseng, Ming-Dou Ker, S.-C. Yang , and A. Shih

Proc. of 2003 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taiwan, Apr. 23-25, 2003, pp. 88-91.

263

“Active device under bond pad to save I/O layout for high-pin-count SOC,”

Ming-Dou Ker, J.-J. Peng, and H.-C. Jiang

Proc. of 2003 IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, Mar. 24-27, 2003. pp. 241-246.

264

“Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed-voltage I/O interface circuits,”

Ming-Dou Ker, H.-C. Hsu, and J.-J. Peng

Proc. of 2003 IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, Mar. 24-27, 2003, pp. 363-368.

265

“Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC’s,”

Ming-Dou Ker, J.-J. Peng, and H.-C. Jiang

Proc. of 2003 IEEE International Conf. on Microelectronics Test Structures (ICMTS), Monterey, California, USA, Mar. 17-20, 2003, pp. 161-166.

266

ESD robustness of LTPS diodes and n-channel TFTs,”

Ming-Dou Ker, T.-K. Tseng, H.-C. Jiang, S.-C. Yang, A. Shih, and Y.-M. Tsai

Proc. of 2003 International Display Manufacturing Conf. & FPD Expo (IDMC), Taipei, Taiwan, Feb. 18-21, 2003, pp. 389-392.

267  

Complementary substrate-triggered SCR devices for on-chip ESD protection circuits,”

Ming-Dou Ker and K.-C. Hsu

Proc. of 2002 IEEE International ASIC/SOC Conf., Rochester, New York, Sep. 25-28, 2002, pp. 229-233.

268  

ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins,”

Ming-Dou Ker, C.-Y. Chang, and Y.-S. Chang

Proc. of 2002 IEEE International ASIC/SOC Conf., Rochester, New York, Sep. 25-28, 2002, pp. 234-238.

269

“Design of negative charge pump circuit with polysilicon diodes in a 0.25-μm CMOS process,”

Ming-Dou Ker, C.-Y. Chang, and H.-C. Jiang

Proc. of 2002 IEEE AP-ASIC Conf., 2002, Taipei, Taiwan, pp. 145-148.

270  

ESD Robustness of Low Temperature Poly-Si TFT’s,”

Ming-Dou Ker, T.-K. Tseng, H.-C. Jiang, and S.-W. Chang

Proc. of 2002 International Workshop on Active-Matrix Liquid-Crystal Displays (AM-LCD), Tokyo, Japan, Jul. 10-12, 2002, pp. 251-254.

271

“Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness,”

Ming-Dou Ker, H.-C. Hsu and J.-J. Peng

Proc. of 2002 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 8-12, 2002, pp. 70-74.

272

“Failure anlaysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution,”

Ming-Dou Ker, J.-J. Peng, and H.-C. Jiang

Proc. of 2002 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 8-12, 2002, pp. 84-89.

273

“Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product,”

I.-C. Lin, C.-Y. Huang, C.-J. Chao, Ming-Dou Ker, S.-Y. Chuan, L.-Y. Leu, F.-C. Chiu, and J.-C. Tseng

Proc. of 2002 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 8-12, 2002, pp. 75-79.

274

“ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness,”

Ming-Dou Ker, W.-Y. Lo, C.-M. Lee, C.-P. Chen, and H.-S. Kao

Proc. of 2002 IEEE Radio Frequency Integrated Circuit Symposium (RFIC), Seattle, Washington, USA, Jun. 2-4, 2002, pp. 427-430. (also in Digest of IEEE MTT-S International Microwave Symposium, vol. 1, 2002, pp. 537-540.)

275

“ESD protection circuits with novel MOS-bounded diode structures,”

Ming-Dou Ker and C.-H. Chuang

Proc. of 2002 IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, USA, May 26-29, 2002, pp. 533-536.

276

“Lathcup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits,”

J.-J. Peng, Ming-Dou Ker, and H.-C. Jiang

Proc. of 2002 IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, USA, May 26-29, 2002, pp. 537-540.

277

“On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process,”

Ming-Dou Ker and K.-C. Hsu

Proc. of 2002 IEEE International Symposium on Circuits and Systems (ISCAS), Scottsdale, Arizona, USA, May 26-29, 2002, pp. 529-532.

278

“ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process,”

Ming-Dou Ker, C.-H. Chuang, K.-C. Hsu, and W.-Y. Lo

Proc. of the 3rd IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, Mar. 18-20, 2002, pp. 331-336.

279

“Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology,”

Ming-Dou Ker and H.-C. Jiang

IEEE 2001 International Conference on Nanotechnology (IEEE-NANO), Maui, Hawaii, USA, Oct. 28 – 30, 2001, pp. 325-330.

280

 

“ESD test methods on integrated circuits: An Overview,”

Ming-Dou Ker, J.-J. Peng, and H.-C. Jiang

Proc. of the 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2001), Malta, Sep. 2 – 5, 2001, Vol. II, pp. 1011-1014.

281

 

“Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC’s,”

Ming-Dou Ker, H.-C. Jiang, J.-J. Peng, and T.-L. Shieh

Proc. of the 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2001), Malta, Sep. 2 – 5, 2001, Vol. I, pp. 113-116.

282

Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18um salicided CMOS process,

M.-D. Ker, C.-H. Chuang, and W.-Y. Lo

Proc. of the 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2001), Malta, Sep. 2 – 5, 2001, Vol. I, pp. 361-364.

283

 

“ESD protection design for CMOS RF integrated circuits,”

Ming-Dou Ker, T.-Y. Chen, and C.-Y. Chang

Proc. of the 23rd Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Portland, Oregon, USA, Sep. 9-13, 2001, pp. 346-354.

284

 

“ESD protection design for mixed-voltage I/O buffer by using stacked-NMOS triggered SCR device,”

 Ming-Dou Ker, C.-H. Chuang, and H.-C. Jiang

Proc. of the 23rd Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Portland, Oregon, USA, Sep. 9-13, 2001, pp. 32-43.

285  

“ESD implantations in 0.18-µm salicided CMOS technology for on-chip ESD protection with layout consideration,”

 Ming-Dou Ker, C.-H. Chuang

Proc. of 2001 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 9-13, 2001, pp. 85-90.

286  

 “Novel diode structures and ESD protection circuits in a 1.8-V 0.15-µm partially-depleted SOI salicided CMOS process,”

Ming-Dou Ker, K.-K. Hung, T.-H.Tang, S.-C. Huang, S.-S. Chen, and M.-C. Wang

Proc. of 2001 International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 9-13, 2001, pp. 91-96.

287  

“Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes,”

Ming-Dou Ker and T.-Y. Chen

Proc. of 2001 IEEE International Symposium on Circuits and Systems (ISCAS), Sydney, Australia, May 6-9, 2001, vol. 4, pp. 758-761.

288

 

“ESD protection design in a 0.18-µm salicide CMOS technology by using substrate-triggered technique,”

Ming-Dou Ker, T.-Y. Chen, and C.-Y. Wu

Proc. of 2001 IEEE International Symposium on Circuits and Systems (ISCAS), Sydney, Australia, May 6-9, 2001, vol. 4, pp. 754-757.

289  

“Level shifters for high-speed 1-V to 3.3-V interfaces in a 0.13-µm Cu-interconnection / low-k CMOS technology,”

W.-T. Wang, Ming-Dou Ker, M.-C. Chiang, and C.-H. Chen

Proc. of 2001 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taiwan, Apr. 18-20, 2001, pp. 307-310.

290  

“On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process,”

C.-Y. Chang and Ming-Dou Ker

Proc. of 2001 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taiwan, Apr. 18-20, 2001, pp. 240-243.

291  

“Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-µm partially-depleted SOI salicide CMOS technology,”

Ming-Dou Ker, K.-K. Hong, T.-Y. Chen, H. Tang, S.-C. Huang, S.-S. Chen, C.-T. Huang, M.-C. Wang, and Y.-T. Loh

Proc. of 2001 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taiwan, Apr. 18-20, 2001, pp. 41-44.

292  

“ESD protection strategy for sub-quarter-micron CMOS technology: gate-driven design versus substrate-triggered design,”

T.-Y. Chen and Ming-Dou Ker

Proc. of 2001 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taiwan, Apr. 18-20, 2001, pp. 232-235.

293

“Compact layout rule extraction for latchup prevention in a 0.25-µm shallow-trench-isolation silicided bulk CMOS process,”

Ming-Dou Ker, W.-Y. Lo, T.-Y. Chen, H. Tang, S.-S. Chen, and M.-C. Wang

Proc. of 2001 IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, Mar. 26-28, 2001, pp. 267-272.

294

“Design on ESD protection circuit with very low and constant input capacitance,”

T.-Y. Chen and Ming-Dou Ker

Proc. of 2001 IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, California, USA, Mar. 26-28, 2001, pp. 247-248. (T.-Y. Chen got the Best Ph.D. Student paper Award).

295

“On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application,”

T.-H. Wang and Ming-Dou Ker

Proc. of the 22th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Anaheim, California, USA, Sep. 26-28, 2000, pp. 266-275.

296

“Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits,”

Ming-Dou Ker, H.-C. Jiang, and C.-Y. Chang

Proc. of 2000 IEEE International ASIC/SOC Conference, Washington, DC, USA, Sep. 13-16, 2000, pp. 293-296. 

297

“Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications,”

Ming-Dou Ker, T.-Y. Chen, C.-Y. Wu, and H.-H. Chang

Proc. of 2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, May 28-31, 2000, vol. 5, pp. 61-64.

298

“New diode string design with very low leakage current for using in power supply ESD clamp circuits,”

Ming-Dou Ker, W.-Y. Lo, and H.-H. Chang

Proc. of 2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, May 28-31, 2000, vol. 5, pp. 69-72.

299

“Hardware / firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard,”

Ming-Dou Ker and Y.-Y. Sung

Proc. of the 21th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Orlando, Florida, USA, Sep. 27-30, 1999, pp. 352-360.

300

“ESD protection design on analog pin with very low input capacitance for RF or current-mode applications,”

Ming-Dou Ker, T.-Y. Chen, C.-Y. Wu, and H.-H. Chang

Proc. of 1999 IEEE International ASIC/SOC Conference, Washington DC, USA, Sep. 15-18, 1999, pp. 352-356.

301

“ESD protection design and verification in a 0.35-μm CMOS ASIC library,”

Ming-Dou Ker, H.-C. Jiang, and J.-J. Peng

Proc. of 1999 IEEE International ASIC/SOC Conference, Washington DC, USA, Sep. 15-18, 1999, pp. 262-266.

302

“New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC’s,”

Ming-Dou Ker, W.-Y. Lo, and C.-Y. Wu

Proc. of 1999 IEEE Custom Integrated Circuits Conference (CICC), San Diego, USA, May 16-19, 1999, pp. 143-146.

303  

“ESD protection design for analog pins with a very low input capacitance,”

Ming-Dou Ker and H.-H. Chang

Proc. of 1999 IEEE Analog VLSI Workshop, Taipei, May 5-7, 1999, pp. 210-205.

304

“ESD buses for whole-chip ESD protection,”

Ming-Dou Ker, H.-H. Chang, and T.-Y. Chen

Proc. of 1999 IEEE International Symposium on Circuits and Systems, Orlando, Florida, USA, May 30-Jun. 2, 1999, pp. 545-548.

305

“Whole-chip ESD protection strategy for CMOS IC’s with multiple mixed-voltage power pins,”

Ming-Dou Ker and H.-H. Chang

Proc. of 1999 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan, Jun. 8-10, 1999, pp. 298-301.

306

“Layout design on bond pads to improve the firmness of bond wire in packaged IC products,”

J.-J. Peng, Ming-Dou Ker, N.-M. Wang, and H.-C. Jiang

Proc. of 1999 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan, Jun. 8-10, 1999, pp. 147-150.

307

“Experimental investigation on the HBM ESD characteristics of CMOS devices in a 0.35-μm silicided process,”

T.-Y. Chen, Ming-Dou Ker, and C.-Y. Wu

Proc. of 1999 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan, Jun. 8-10, 1999, pp. 35-38.

308

“How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,”

Ming-Dou Ker and H.-H. Chang

Proc. of the 20th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, Nevada, USA, Oct. 6-8, 1998, pp. 72-85.

309

“Electrostatic discharge protection circuits in CMOS IC’s using the lateral SCR devices : an overview,”

Ming-Dou Ker

Proc. of 1998 IEEE International Conference on Electronics, Circuits and Systems, Lisboa, Portugal, Sep. 7-10, 1998, pp. 325-328.

310

“CMOS on-chip ESD protection design with substrate-triggering technique,”

Ming-Dou Ker, T.-Y. Chen, and C.-Y. Wu

Proc. of 1998 IEEE International Conference on Electronics, Circuits and Systems, Lisboa, Portugal, Sep. 7-10, 1998, pp. 273-276.

311

“Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection,”

Ming-Dou Ker and H.-H. Chang

Proc. of 1998 IEEE Custom Integrated Circuits Conference (CICC), Santa Clara, California, USA, May 11-14, 1998, pp. 541-544.

312

“Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology,”

Ming-Dou Ker and J.-J. Peng

Proc. of 1998 IEEE Custom Integrated Circuits Conference (CICC), Santa Clara, California, USA, May 11-14, 1998, pp. 537-540.

313

“Dynamic-floating-gate design for output ESD protection in a 0.35-μm CMOS cell library,”

Ming-Dou Ker, H.-H. Chang, C.-C. Wang, H.-R. Yeng, and Y.-F. Tsao

Proc. of 1998 IEEE International Symposium on Circuits and Systems, Monterey, California, USA, May 31-Jun. 3, 1998, vol.2, pp. 216-219.

314

“Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology,”

Ming-Dou Ker, T.-Y. Chen, C.-Y. Wu, H. Tang, K.-C. Su, and S.-W. Sun

Proc. of 1998 IEEE International Symposium on Circuits and Systems, Monterey, California, USA, May 31-Jun. 3, 1998, vol.2, pp. 212-215.

315  

“ESD protection design in TSMC 0.35-μm CMOS cell library,”

Ming-Dou Ker, H.-H. Chang, C.-C. Wang, and H.-R. Yeng

Proc. of 1998 International Conference on Computer Systems Technology for Industrial Applications--Chip Technology, Taiwan, Apr. 8-10, 1998, pp. 63-67.

316

“ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices,”

Ming-Dou Ker

Proc. of the 10th Annual IEEE International ASIC Conference & Exhibits, Portland, Oregon, USA, Sep. 7-10, 1997, pp. 283-286.

317

“Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries,”

Ming-Dou Ker, S.-M. Hsiao, and J.-H. Lin

Proc. of the 10th Annual IEEE International ASIC Conference & Exhibits, Portland, Oregon, USA, Sep. 7-10, 1997, pp. 125-129.

318

“Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC’s with the substrate-triggering technique,”

Ming-Dou Ker, T.-Y. Chen, and C.-Y. Wu

Proc. of the 10th Annual IEEE International ASIC Conference & Exhibits, Portland, Oregon, USA, Sep. 7-10, 1997, pp. 287-290.

319

“New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area,”

Ming-Dou Ker, T.-Y. Chen, and C.-Y. Wu

Proc. of 1997 International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, Jul. 21-25, 1997, pp. 103-108.

320

“Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection,”

Ming-Dou Ker

Proc. of 1997 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan, Jun. 3-5, 1997, pp. 69-73.

321

“Layout verification for submicron CMOS cell libraries to improve ESD/latchup reliability,”

Ming-Dou Ker, S.-M. Hsiao, and J.-H. Lin

Proc. of 1997 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan, Jun. 3-5, 1997, pp. 343-347.

322

 

“Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability,”

Ming-Dou Ker, C.-Y. Wu, and T.-Y. Chen

Proc. of 1997 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan, Jun. 3-5, 1997, pp. 45-49.

323

“Efficient output ESD protection of high-speed SRAM IC with well-couple technique in sub-micron CMOS technology,”

C.-N. Wu, Ming-Dou Ker, et al

Proc. of 1997 IEEE International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, Taiwan, Jun. 3-5, 1997, pp. 40-44.

324

“Whole-chip ESD protection design for submicron CMOS VLSI,”

Ming-Dou Ker and S.-C. Liu

Proc. of 1997 IEEE International Symposium on Circuits and Systems, Hong Kong, Jun. 9-12, 1997, pp. 1920-1923.

325

 “Whole-chip ESD protection scheme for CMOS mixed-mode IC’s in deep-submicron CMOS technology,”

Ming-Dou Ker, C.-Y. Wu, H.-H. Chang, and T.-S. Wu

Proc. of 1997 IEEE Custom Integrated Circuits Conference (CICC), Santa Clara, CA, USA, May 5-8, 1997, pp. 31-34.

326

“Novel octagonal device structure for output transistors in deep-submicron low-voltage CMOS technology,”

Ming-Dou Ker and T.-S. Wu

Technical Digest of IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Dec. 8-11, 1996, pp. 889-892.

327  

“Whole-chip ESD protection design for submicron CMOS technology,”

Ming-Dou Ker and S.-C. Liu

Proc. of 1996 International Electron Devices and Materials Symposium, Hsinchu, Taiwan, Dec.16-20, 1996, pp. 55-58.

328  

“Multiple-cell square-type layout design for output transistors in deep-submicron low-voltage CMOS IC’s to save silicon area,”

Ming-Dou Ker, C.-C. Huang, and C.-Y. Wu

Proc. of 1996 International Electron Devices and Materials Symposium, Hsinchu, Taiwan, Dec.16-20, 1996, pp. 181-184.

329  

“Unexpected ESD damage on internal circuits of sub-μm CMOS technology,”

C.-N. Wu, Ming-Dou Ker, et al

Proc. of 1996 International Electron Devices and Materials Symposium, Hsinchu, Taiwan, Dec.16-20, 1996, pp. 143-146.

330

Efficient output ESD protection for 0.5-μm high-speed CMOS SRAM IC with well-coupled technique,

Ming-Dou Ker and C.-N. Wu

Proc. of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, the Netherlands, Oct. 8-11, 1996, (Microelectronics and Reliability, vol.36, no.11/12, pp. 1731-1734).

331

ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC’s,

Ming-Dou Ker and T.-L. Yu

Proc. of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Netherlands, Oct. 8-11, 1996, (Microelectronics and Reliability, vol.36, no.11/12, pp. 1727-1730).

332

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology,

Ming-Dou Ker, C.-Y. Wu, H.-H. Chang, C.-C. Huang, C.-N. Wu, and T.-L. Yu

Proc. of 1996 IEEE Hong Kong Electron Devices Meeting, Hong Kong, Jun. 29, 1996. pp. 98-101.

333

Area-efficient layout design for output transistors with consideration of ESD reliability,

Ming-Dou Ker, C.-Y. Wu, C.-C. Huang, H.-H. Chang, C.-N. Wu, and T.-L. Yu

Proc. of 1996 IEEE Hong Kong Electron Devices Meeting, Hong Kong, June 29, 1996. pp. 94-97.

334

ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure,

Ming-Dou Ker, H.-H. Chang, and C.-Y. Wu

Technical Digest of IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, Dec. 10-13, 1995, pp. 543-546.

335

Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS ICs,

Ming-Dou Ker, C.-Y. Wu, T. Cheng, H.-H. Chang, M.. Wu, and T.-L. Yu

Proc. of the 4th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, Oct. 24-28, 1995, pp. 193-195.

336

Area-efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC,

Ming-Dou Ker, K.-F. Wang, M.-C. Joe, Y.-H. Chu, and T.-S. Wu

Proc. of the 8th IEEE International ASIC Conference and Exhibit, Austin, Texas, USA, Sep. 18-22, 1995, pp. 123-126.

337

On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology,

Ming-Dou Ker, C.-Y. Wu, T. Cheng, M. Wu, and T.-L. Yu

Proc. of the 8th IEEE International ASIC Conference and Exhibit, Austin, Texas, USA, Sep. 18-22, 1995, pp. 135-138.

338  

Modeling the positive-feedback regenerative process of CMOS transient-induced latchup,

Ming-Dou Ker, T.-S. Wu, and C.-Y. Wu

Proc. of 1995 IEEE Singapore International Conference on Signal Processing, Circuits and Systems, Jul. 3-7, 1995, pp. 240-245.

339

Complementary-LVTSCR ESD protection scheme for submicron CMOS ICs,

Ming-Dou Ker, C.-Y. Wu, H.-H. Chang, T. Cheng, and T.-S. Wu

Proc. of 1995 IEEE International Symposium on Circuits and Systems, Seattle, USA, Apr.29-May 3, 1995, pp. 833-836.

340

Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins,

Ming-Dou Ker, C.-Y. Wu, T. Cheng, M. Wu, T.-L. Yu, and A. Wang

Proc. of 1994 IEEE International Integrated Reliability Workshop (IRW), USA, Oct. 16-19, 1994, pp. 124-128.

341

An on-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs,

Ming-Dou Ker, C.-Y. Wu, H.-C. Jiang, C.-Y. Lee, J. Ko, and P. Hsue

Proc. of the 37th IEEE Midwest Symposium on Circuits and Systems, Louisiana, USA, Aug. 3-5, 1994, pp. 1145-1148.

342  

A latchup-free fully-protected ESD protection circuit for input pads of submicron CMOS ICs,

Ming-Dou Ker, T.-S. Wu, C.-Y. Wu, K.-F. Wang, L.-M. Yang, and J.-S. Wang

Proc. of the 5th International Symposium on IC Technology, Systems & Applications, Singapore, Sep. 15-17, 1993, pp. 234-238.

343

 

The large-signal positive transient pole and its effect on CMOS transient latchup,

Ming-Dou Ker, C.-Y. Wu, C.-Y. Lee, and J. Ko

Proc. of 1992 International Electron Devices and Materials Symposium, Taipei, Taiwan, Nov. 1-4, 1992, pp. 64-67.

344  

Double low-voltage triggering parasitic lateral SCR structures to improve CMOS on-chip ESD/EOS protection capability,

Ming-Dou Ker, C.-Y. Wu, and C.-Y. Lee

Proc. of the 3rd International Conference on Solid State and Integrated-Circuit Technology, Beijing, China, Oct. 18-24, 1992, pp. 630-633.

345  

A novel CMOS ESD/EOS protection circuit with full-SCR structures,

Ming-Dou Ker, C.-Y. Wu, and C.-Y. Lee

Proc. of 1992 Electrical Overstress/Electrostatic Discharge Symposium, Dallas, Texas, USA, Sep. 15-18, 1992, pp. 258-264.

346

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI,

C.-Y. Wu, Ming-Dou Ker, C.-Y. Lee, J. Ko, and L. Lin

Proc. of 1991 IEEE Custom Integrated Circuits Conference (CICC), May 12-15, 1991, pp. 27.2.1-27.2.4.

347  

A new analytical criterion for CMOS transient latchup,

C.-Y. Wu, Ming-Dou Ker, C.-Y. Lee, J. Ko, and L. Lin

Proc. of 1990 International Electron Devices and Materials Symposium, Taiwan, 1990, pp. 18-21.